The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2024
Filed:
Jul. 22, 2021
Applicant:
Vmware, Inc., Palo Alto, CA (US);
Inventors:
Marcos Kawazoe Aguilera, Mountain View, CA (US);
Renu Raman, Palo Alto, CA (US);
Pratap Subrahmanyam, Saratoga, CA (US);
Praveen Vegulla, Cupertino, CA (US);
Rajesh Venkatasubramanian, San Jose, CA (US);
Assignee:
VMware LLC, Palo Alto, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/4856 (2013.01); G06F 9/5027 (2013.01); G06F 12/08 (2013.01); G06F 2209/505 (2013.01); G06F 2212/1044 (2013.01);
Abstract
Disclosed are various embodiments for optimized memory tiering. An ideal tier size for a first memory and an ideal tier size for a second memory can be determined for a process. Then, a host computing device can be identified that can accommodate the ideal tier size for the first memory and the second memory. Subsequently, the process can be assigned to the host computing device.