The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Mar. 13, 2024
Applicant:

Essencore Limited, Wanchai, HK;

Inventors:

Chan Ho Sohn, Seoul, KR;

Ting Lun Ou, Taipei, TW;

Kwang Soo Moon, Seoul, KR;

Assignee:

ESSENCORE LIMITED, Wanchai, HK;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/00 (2023.01); G06F 12/02 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); H01L 24/42 (2013.01); H10B 41/00 (2023.02); H01L 22/22 (2013.01); H01L 23/49811 (2013.01); H01L 2224/42 (2013.01); H01L 2224/48155 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/484 (2013.01); H01L 2224/85 (2013.01); H05K 2203/049 (2013.01);
Abstract

Provided is a method of processing a NAND flash memory device including at least one NAND flash memory and a memory controller configured to control the at least one NAND flash memory. The method includes etching a portion of a first substrate of the NAND flash memory device to expose a wire connecting the at least one NAND flash memory and the memory controller to each other, dividing the wire into a first wire and a second wire by etching a first area of the etched first substrate, and connecting, to a second substrate, the first wire to which the at least one NAND flash memory is connected.


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