The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Feb. 15, 2023
Applicant:

Siliconch Systems Pvt Ltd, Karnataka, IN;

Inventors:

Rakesh Kumar Polasa, Karnataka, IN;

Vinay Sadrhalli Nagendra Patel, Karnataka, IN;

Shubham Paliwal, Uttar Pradesh, IN;

Alagesan Mani, Tamil Nadu, IN;

Assignee:

SILICONCH SYSTEMS PVT LTD, Karnataka, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 11/273 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2236 (2013.01); G06F 11/273 (2013.01);
Abstract

The present disclosure provides a system () and a method () for real-time debugging of a processor (). The system includes a debugging unit () configured to receive a first set of instructions from the processor. The first set of instructions includes a set of function calls and/or a set of jump instructions. The debugging unit further includes a skip list unit () including a skip set of instructions. The skip list unit is configured to remove, from the first set of instructions, the skip set of instructions to generate a second set of instructions. The debugging unit includes a loop exclusion unit () configured to determine loops of instructions based on loop unrolling of the second set of instructions to generate a third set of instructions by removing loops of instructions from the second set of instructions. The debugging unit is configured to store the third set of instructions.


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