The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2024

Filed:

Mar. 24, 2022
Applicant:

Smart Modular Technologies, Inc., Newark, CA (US);

Inventors:

Robert Tower Frey, Newark, CA (US);

Kelvin Marino, Newark, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 1/30 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 1/30 (2013.01); G06F 11/0772 (2013.01); G06F 11/0793 (2013.01); G06F 11/1402 (2013.01); G06F 13/4282 (2013.01);
Abstract

Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.


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