The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2024

Filed:

Oct. 18, 2023
Applicant:

Quantum-si Incorporated, Branford, CT (US);

Inventors:

Eric A. G. Webster, Santa Clara, CA (US);

Todd Rearick, Cheshire, CT (US);

Thomas Raymond Thurston, Guilford, CT (US);

Assignee:

Quantum-Si Incorporated, Branford, CT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01J 1/44 (2006.01); B01J 19/00 (2006.01); H01L 27/146 (2006.01); H01L 27/148 (2006.01);
U.S. Cl.
CPC ...
G01J 1/44 (2013.01); B01J 19/0046 (2013.01); H01L 27/14683 (2013.01); H01L 27/14818 (2013.01); H01L 27/14825 (2013.01); B01J 2219/00504 (2013.01); B01J 2219/00576 (2013.01); B01J 2219/00587 (2013.01); B01J 2219/00689 (2013.01); B01J 2219/00698 (2013.01); G01J 2001/446 (2013.01);
Abstract

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.


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