The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Dec. 22, 2021
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventor:

Luca Sayadi, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/43 (2006.01); H01L 29/47 (2006.01); H01L 29/812 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 29/432 (2013.01); H01L 29/475 (2013.01); H01L 29/812 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01);
Abstract

In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d, a lower p-doped Group III nitride layer having a thickness dand including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped AlGaN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness dof the lower p-doped Group III nitride layer is larger than the thickness dof the upper p-doped GaN layer.


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