The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

May. 12, 2021
Applicant:

Nuvoton Technology Corporation Japan, Kyoto, JP;

Inventors:

Katsuhiko Kawashima, Hyogo, JP;

Yusuke Kanda, Toyama, JP;

Kenichi Miyajima, Toyama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66462 (2013.01); H01L 29/2003 (2013.01); H01L 29/404 (2013.01); H01L 29/41725 (2013.01); H01L 29/4232 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01);
Abstract

A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.


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