The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2024
Filed:
Feb. 14, 2022
Electronics and Telecommunications Research Institute, Daejeon, KR;
Soo Cheol Kang, Daejeon, KR;
Hyun Wook Jung, Daejeon, KR;
Seong IL Kim, Daejeon, KR;
Hae Cheon Kim, Daejeon, KR;
Youn Sub Noh, Daejeon, KR;
Ho Kyun Ahn, Daejeon, KR;
Sang Heung Lee, Daejeon, KR;
Jong Won Lim, Daejeon, KR;
Sung Jae Chang, Daejeon, KR;
Il Gyu Choi, Daejeon, KR;
ELECTRONICS AND TELECOMMINICATIONS RESEARCH INSTITUTE, Daejeon, KR;
Abstract
A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.