The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Oct. 06, 2020
Applicant:

Vitesco Technologies Gmbh, Regensburg, DE;

Inventors:

Christina Quest-Matt, Munich, DE;

Detlev Bagung, Munich, DE;

Daniela Wolf, Munich, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H05K 1/02 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3736 (2013.01); H01L 23/3737 (2013.01); H01L 23/49822 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/83801 (2013.01); H05K 1/0206 (2013.01); H05K 3/341 (2013.01);
Abstract

A power semiconductor component includes at least one power semiconductor device disposed within a housing and a heat sink having an area a exposed on a first surface of the housing. A wiring substrate has a first main surface and a second main surface. A heat dissipation region with increased thermal conductivity is disposed on the second main surface. The heat dissipation region has an area A on the second main surface, and a<A. The housing with the power semiconductor device is disposed on the second main surface of the wiring substrate in such a way that the heat sink is disposed completely on the heat dissipation region and is connected thereto by way of a solder layer. A method for producing a power semiconductor component is also provided.


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