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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12165942 B1

PDFFull Text
Date of Patent:
Dec. 10, 2024

Filed:

Jan. 27, 2022

Integrated circuit packages with cavities and methods of manufacturing the same

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jesus Bajo Bautista, Jr., Baguio, PH;

Jeffrey Dorado Emperador, Baguio, PH;

Francis Masiglat de Vera, Baguio, PH;

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Dawn Jos

Frank D. Cimino

Primary Examiner:

Mohammad M Hoque

Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/315 (2013.01); H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/4951 (2013.01); H01L 23/49575 (2013.01); H01L 23/49586 (2013.01); H01L 23/49827 (2013.01); H01L 23/49861 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01);
Abstract

Integrated circuit packaging with cavities and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor die and a housing enclosing portions of the semiconductor die. The housing defines an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material. The example apparatus includes a second material disposed within the opening to block exposure of the semiconductor die to the external environment.

Find Patent Forward Citations

Bautista, Jr., Jesus. (2024). Integrated circuit packages with cavities and methods of manufacturing the same (U.S. Patent No. 12165942). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12165942

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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