The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Aug. 26, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Naoki Kimura, Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/30 (2006.01); G06F 13/16 (2006.01); G11C 5/14 (2006.01); G11C 16/04 (2006.01); G06F 3/06 (2006.01); G06F 13/14 (2006.01); G06F 13/42 (2006.01); G11C 11/4072 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G06F 13/1668 (2013.01); G11C 5/147 (2013.01); G11C 16/0483 (2013.01); G06F 3/0607 (2013.01); G06F 3/0625 (2013.01); G06F 3/0634 (2013.01); G06F 3/0688 (2013.01); G06F 13/14 (2013.01); G06F 13/4221 (2013.01); G11C 5/14 (2013.01); G11C 11/4072 (2013.01); G11C 11/4074 (2013.01);
Abstract

A memory system includes: a connector including a first terminal and a second terminal, each of which is capable of being connected to a host device; a non-volatile memory; and a controller connected between the connector and the non-volatile memory. The controller includes: a control circuit including a first node and a second node; a first signal line connected between the first terminal and the first node and capable of being pulled up to a first power level or a second power level; a second signal line connected to the second terminal; and a first resistance element including one end connected to the first signal line and the other end connected to the second signal line.


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