The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Nov. 29, 2021
Applicant:

Japan Science and Technology Agency, Kawaguchi, JP;

Inventors:

Satoshi Sugahara, Tokyo, JP;

Daiki Kitagata, Tokyo, JP;

Shuichiro Yamamoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 11/56 (2006.01); G11C 14/00 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 11/56 (2013.01); G11C 14/0054 (2013.01); H03K 3/356 (2013.01); G11C 14/0081 (2013.01);
Abstract

An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.


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