Multi-processor system with dynamically selectable multi-stage firmware image sequencing and distributed processing system thereof

Abstract

A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.