The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2024

Filed:

Feb. 14, 2023
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Vishwajit Babasaheb Bugade, Kolhapur, IN;

Anand Kumar Sinha, Noida, IN;

Krishna Thakur, GautamBudh Nagar, IN;

Siyaram Sahu, Bari Raisen, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); G06F 1/08 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); H03K 5/01 (2013.01); H03K 2005/00013 (2013.01); H03K 2005/00286 (2013.01);
Abstract

A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.


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