The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2024
Filed:
Aug. 04, 2021
Applicant:
Socionext Inc., Kanagawa, JP;
Inventor:
Isaya Sobue, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); B82Y 10/00 (2011.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 27/0922 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01);
Abstract
A layout structure of a capacitive element using a complementary FET (CFET) and having a high breakdown voltage is provided. In the capacitive element, first and second transistors overlap as viewed in plan, and the gates thereof are mutually connected. Third and fourth transistors overlap as viewed in plan, and the gates thereof are mutually connected. Nodes of the first and third transistors are mutually connected through a local interconnect, and nodes of the second and fourth transistors are mutually connected through a local interconnect.