The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

Dec. 09, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Richard Allen Faust, Dallas, TX (US);

Robert Martin Higgins, Plano, TX (US);

Anagha Shashishekhar Kulkarni, Richardson, TX (US);

Jonathan Philip Davis, Allen, TX (US);

Sudtida Lavangkul, Murphy, TX (US);

Andrew Frank Burnett, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); H01L 21/823475 (2013.01); H01L 24/05 (2013.01); H01L 2224/03009 (2013.01); H01L 2224/03505 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03616 (2013.01); H01L 2224/03848 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/0508 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05164 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05169 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05184 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/059 (2013.01); H01L 2924/20106 (2013.01); H01L 2924/20107 (2013.01); H01L 2924/20108 (2013.01); H01L 2924/20109 (2013.01); H01L 2924/2011 (2013.01);
Abstract

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.


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