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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12159843 B1

PDFFull Text
Date of Patent:
Dec. 03, 2024

Filed:

Sep. 10, 2021

Semiconductor device

Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Daisuke Kawamura, Kiyosu, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Mohammad A Rahman

Assistant Examiner:

Eric Manuel Mulero Flores

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device according to an embodiment includes a lower layer wiring and a dummy wiring arranged in a first hierarchy, a contact arranged in a second hierarchy above the first hierarchy and connected to the lower layer wiring, and first and second plate-like portions arranged in the second hierarchy, extending in a stacking direction of each layer belonging to the second hierarchy and in a first direction intersecting with the stacking direction, and sandwiching the contact in a second direction intersecting with the stacking direction and the first direction at a position away from the contact, and the dummy wiring has at least three edges arranged at respective positions overlapping with one of the first and second plate-like portions in the stacking direction, and an orientation in which at least one of the three edges intersects with the first or second plate-like portion differs as viewed from the stacking direction from orientations in which the other edges intersect with the first or second plate-like portion.

Find Patent Forward Citations

Kawamura, Daisuke. (2024). Semiconductor device (U.S. Patent No. 12159843). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12159843

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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