The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

May. 19, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Mir Im, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 8/14 (2006.01); G11C 11/408 (2006.01); G11C 11/4097 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4097 (2013.01); G11C 8/14 (2013.01); G11C 11/4085 (2013.01); H01L 27/088 (2013.01); H10B 12/00 (2023.02);
Abstract

A semiconductor device according to an embodiment of the present disclosure includes a write transistor and a read transistor disposed over a substrate. The write transistor includes a write word line disposed on a plane that is substantially parallel to a surface of the substrate over the substrate, a write gate dielectric layer disposed over the write word line, a write channel layer disposed over the write gate dielectric layer, and a write bit line disposed over the substrate and extending in a direction substantially perpendicular to a surface of the substrate, and electrically connected to one end of the write channel layer. The read transistor includes a read channel layer disposed on the plane over the substrate, a read gate dielectric layer disposed over the read channel layer, and a read gate electrode layer disposed over the read gate dielectric layer and electrically connected to the other end of the write channel layer.


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