Clock gating circuit for avoiding out-of-spec clock operations in self-timed circuits

Abstract

A clock gating method and circuit for avoiding out-of-spec clock operations. The circuit comprises a clock gating section that gates a clock signal according to an enabling signal generated by an enabling signal controller, the enabling signal controller generating the enabling signal according to a set signal and a reset signal. The circuit further comprises a set signal generator that generates the set signal, a reset signal generator that generates the reset signal, and a feedback section that uses the enabling signal to generate the feedback signal for the reset signal generator. The reset signal generator generates the reset signal by using the feedback signal. The enabling signal controller further generates an acknowledgement signal having a high signal during a blocking period when the clock signal is blocked and utilizes the acknowledgement signal as an announcement to a higher circuit that the clock signal is blocked.