The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2024

Filed:

Apr. 14, 2023
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chun-Yi Kuo, Hsinchu, TW;

Po-Lin Chen, Hsinchu, TW;

Yu-Cheng Lo, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31726 (2013.01); G01R 31/318533 (2013.01);
Abstract

A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.


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