The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2024
Filed:
May. 05, 2022
Applicant:
Zeno Semiconductor, Inc., Sunnyvale, CA (US);
Inventor:
Yuniarto Widjaja, Cupertino, CA (US);
Assignee:
Zeno Semiconductor, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 7/00 (2006.01); G11C 8/10 (2006.01); G11C 8/16 (2006.01); G11C 11/40 (2006.01); G11C 11/403 (2006.01); G11C 11/405 (2006.01); H01Q 1/22 (2006.01); H10B 12/00 (2023.01); H10B 12/10 (2023.01); H01L 27/105 (2023.01);
U.S. Cl.
CPC ...
H10B 12/20 (2023.02); G11C 7/00 (2013.01); G11C 8/10 (2013.01); G11C 8/16 (2013.01); G11C 11/40 (2013.01); G11C 11/403 (2013.01); G11C 11/405 (2013.01); H01Q 1/2283 (2013.01); H10B 12/10 (2023.02); H01L 27/105 (2013.01);
Abstract
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.