The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Nov. 22, 2019
Applicant:

C/o Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Daisuke Ito, Kanagawa, JP;

Kenichi Murata, Kanagawa, JP;

Toshiko Hayashi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 27/14636 (2013.01); H01L 27/14649 (2013.01); H01L 27/1469 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01);
Abstract

A first semiconductor element according to one embodiment of the present disclosure includes an element substrate including an element region, a peripheral region, a readout circuit substrate, a first electrode, a second electrode, and an insulating layer. A wiring layer and a first semiconductor layer including a compound semiconductor material are provided as a stack in the element region. The peripheral region is outside the element region. The readout circuit substrate is opposed to the first semiconductor layer with the wiring layer interposed therebetween, and is electrically coupled to the first semiconductor layer with the wiring layer interposed therebetween. The first electrode is provided in the wiring layer and is electrically coupled to the first semiconductor layer. The second electrode is opposed to the first electrode with the first semiconductor layer interposed therebetween. The insulating layer is provided on the second electrode and has a non-reducing property.


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