The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Sep. 23, 2022
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Young Mok Jeong, Icheon-si Gyeonggi-do, KR;

Min Gyu Park, Icheon-si Gyeonggi-do, KR;

Min Su Park, Icheon-si Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Icheon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1093 (2013.01); G11C 7/1087 (2013.01); G11C 7/1096 (2013.01);
Abstract

A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.


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