The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Dec. 20, 2022
Applicant:

Nxp B.v., Eindhoven, NL;

Inventor:

Soenke Ostertun, Wedel, DE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/24 (2006.01); G11C 29/40 (2006.01); G11C 29/46 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G11C 7/24 (2013.01); G11C 29/40 (2013.01); G11C 2029/1204 (2013.01);
Abstract

In a non-volatile memory (NVM) system of a memory device, a memory controller connected to memory cell arrays of the NVM system is configured to perform the steps of selecting a memory cell to test, energizing a test circuit connected to the memory cell under a first biasing condition, reading a measurement of an electrical property of the memory cell, and determining, based on the measurement, whether the memory cell is formed or unformed. In embodiments, the system and method include protecting the test circuit from attack by validating the results of the testing. The memory controller is further configured to energize the test circuit under a second biasing condition that produces a known test result whether the memory cell is formed or unformed; if the result of the second test is not the expected result, the memory controller determines that the testing circuit is malfunctioning or under attack.


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