The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Jul. 27, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Steve Hengchen Hsu, San Diego, CA (US);

Thirunathan Sutharsan, San Diego, CA (US);

Mohanned Omar Sinnokrot, San Diego, CA (US);

On Wa Yeung, San Diego, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 3/06 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3838 (2013.01); G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0664 (2013.01); G06F 3/0676 (2013.01); G06F 3/0677 (2013.01); G06F 3/0679 (2013.01); G06F 9/30036 (2013.01);
Abstract

A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. The processing engines can be arranged in pipelines, with different processing engines executing different steps in a sequence of operations. Flow control or data synchronization between pipeline stages can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management. Firmware instructions can define data flow by reference to a virtual address space associated with pipeline buffers. A hardware interlock controller within the pipeline can track and enforce the data dependencies for the pipeline.


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