The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

May. 09, 2023
Applicant:

Icometrue Company Ltd., Zhubei, TW;

Inventors:

Mou-Shiung Lin, Hsinchu, TW;

Jin-Yuan Lee, Hsinchu, TW;

Assignee:

iCometrue Company Ltd., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/34 (2020.01); G05B 19/042 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 11/412 (2006.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01); H03K 19/177 (2020.01); H03K 19/1776 (2020.01); H10B 20/00 (2023.01); H10B 41/35 (2023.01);
U.S. Cl.
CPC ...
G06F 30/34 (2020.01); G05B 19/0423 (2013.01); G06F 3/0605 (2013.01); G06F 3/0659 (2013.01); G11C 7/1012 (2013.01); G11C 7/1045 (2013.01); G11C 7/106 (2013.01); G11C 11/412 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H03K 19/177 (2013.01); H03K 19/1776 (2013.01); H10B 20/65 (2023.02); H10B 41/35 (2023.02); G05B 2219/15057 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.


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