The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

May. 19, 2020
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Linhong Han, Beijing, CN;

Meng Zhang, Beijing, CN;

Yi Zhang, Beijing, CN;

Pengfei Yu, Beijing, CN;

Shikai Qin, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); G09G 3/00 (2006.01); H01L 51/00 (2006.01); H01L 51/56 (2006.01); H10K 59/121 (2023.01); H10K 59/122 (2023.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01); H10K 59/88 (2023.01); H10K 71/00 (2023.01); H10K 71/70 (2023.01);
U.S. Cl.
CPC ...
H10K 59/88 (2023.02); G09G 3/006 (2013.01); H10K 59/1216 (2023.02); H10K 59/122 (2023.02); H10K 59/124 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10K 71/70 (2023.02); G09G 2300/0809 (2013.01); G09G 2330/12 (2013.01);
Abstract

The present disclosure provides a display panel, a display device, a test method, and a crack detection method. The display panel includes: a base substrate including a display area and a peripheral area; a plurality of sub-pixels in the display area; a plurality of data signal lines in the display area and electrically connected to the plurality of sub-pixels; a plurality of signal transmission lines in the peripheral area and electrically connected to the plurality of data signal lines; a plurality of multiplexers in the peripheral area; and a first test circuit on a side of the plurality of multiplexers away from the plurality of sub-pixels. The first test circuit includes a plurality of test components, each of at least a portion of the plurality of test components being electrically connected to at least two multiplexers.


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