The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Oct. 29, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Anand Seshadri, Richardson, TX (US);

Kemal Tamer San, Plano, TX (US);

Sunil Kumar Dusa, Plano, TX (US);

Michael Ball, Richardson, TX (US);

Akram A. Salman, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 23/525 (2006.01); H10B 20/20 (2023.01);
U.S. Cl.
CPC ...
H10B 20/20 (2023.02); G11C 17/165 (2013.01); G11C 17/18 (2013.01); H01L 23/5256 (2013.01);
Abstract

An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.


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