The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Apr. 23, 2021
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Tsutomu Imoto, Kanagawa, JP;

Yusuke Ikeda, Tokyo, JP;

Atsumi Niwa, Kanagawa, JP;

Atsushi Suzuki, Kanagawa, JP;

Shinichirou Etou, Kanagawa, JP;

Kenichi Takamiya, Kanagawa, JP;

Takuya Maruyama, Kanagawa, JP;

Ren Hiyoshi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/47 (2023.01); H04N 25/60 (2023.01); H04N 25/77 (2023.01); H04N 25/78 (2023.01);
U.S. Cl.
CPC ...
H04N 25/47 (2023.01); H04N 25/77 (2023.01); H04N 25/78 (2023.01); H04N 25/60 (2023.01);
Abstract

Suppressing a dead period at the time of mode switching. A solid-state imaging device includes: a plurality of pixels () that each outputs a luminance change of incident light; and a detection circuit () that outputs an event signal based on the luminance change output from each of the pixels, in which each of the pixels includes: a photoelectric conversion element () that generates a charge according to an incident light amount; a logarithmic conversion circuit () that is connected to the photoelectric conversion element and converts a photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; and a first transistor () having a drain connected to a sense node of the logarithmic conversion circuit.


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