The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

May. 04, 2023
Applicant:

Silicon Motion, Inc., Zhubei, TW;

Inventors:

Shiuan-Hao Kuo, New Taipei, TW;

Hung-Jen Huang, Taichung, TW;

Assignee:

SILICON MOTION, INC., Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/37 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1137 (2013.01); H03M 13/1108 (2013.01); H03M 13/3746 (2013.01); H03M 13/6575 (2013.01);
Abstract

A method and apparatus for decoding a Low-Density Parity-Check (LDPC) code whereby the apparatus comprises an LDPC decoder comprising variable-node calculation circuitry and check-node calculation circuitry: the check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on a codeword and a parity check matrix to calculate a plurality of first syndromes in a first-stage state. The variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm to generate variable nodes, and calculate soft bits for the variable nodes in a second-stage state. The check-node calculation circuitry is arranged to perform the modulo 2 multiplication on the variable nodes and the parity check matrix to calculate second syndromes in the second-stage. When second syndromes indicate that the previously generated variable nodes are incorrect, a third stage state is repeated until decoding succeeds or a total number of iterations exceeds a threshold.


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