The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Mar. 10, 2023
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Masataka Ikeda, Tokyo, JP;

Hirotaka Hayashi, Tokyo, JP;

Hitoshi Tanaka, Tokyo, JP;

Assignee:

JAPAN DISPLAY INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); G02F 1/167 (2019.01); G02F 1/16766 (2019.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); G02F 1/167 (2013.01); G02F 1/16766 (2019.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 28/60 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01);
Abstract

According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.


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