The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Sep. 29, 2021
Applicant:

Shenzhen Goodix Technology Co., Ltd., Shenzhen, CN;

Inventors:

Yunfei Gao, San Diego, CA (US);

Tae Seok Oh, San Diego, CA (US);

Jinwen Xiao, San Diego, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14614 (2013.01); H01L 27/14645 (2013.01); H01L 27/14689 (2013.01); H01L 29/42356 (2013.01); H01L 29/4236 (2013.01); H01L 29/66621 (2013.01); H01L 29/66628 (2013.01); H01L 29/7813 (2013.01);
Abstract

A trench-gate source-follower (TGSF) transistor is described, such as for integration with image sensor pixels. The TGSF transistor is at least partially built into a trench etched into a substrate. A contiguous doped region is implanted around the inner walls of the trench to form a buried-trench current channel. A trench-gate is formed to have at least a buried portion that fills the volume of the trench. A gate oxide layer can be disposed between the buried portion of the trench-gate and the buried-trench current channel. Drain and source regions are formed on either end of the trench-gate. Activating the trench-gate causes current to flow between the drain and source regions via the buried-trench current channel around the buried portion of the trench-gate. The geometry of the buried-trench current channel can effectively increase the width of the active region of the source-follower transistor without increasing its physical layout width.


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