The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Jan. 25, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Scott Robert Summerfelt, Garland, TX (US);

Thomas Dyer Bonifield, Dallas, TX (US);

Sreeram Subramanyam Nasum, Bangalore, IN;

Peter Smeys, San Jose, CA (US);

Benjamin Stassen Cook, Los Gatos, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/762 (2006.01); H01L 21/78 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/564 (2013.01); H01L 21/76232 (2013.01); H01L 21/78 (2013.01); H01L 23/293 (2013.01); H01L 23/3121 (2013.01); H01L 23/642 (2013.01);
Abstract

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.


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