High-bandwidth ddr dimm, memory system, and operation method thereof

Abstract

The present disclosure discloses a high-bandwidth double data rate (DDR) dual-in-line memory module (DIMM), a memory system, and an operation method of the memory system. The high-bandwidth DDR DIMM includes a first sub-channel, a second sub-channel, a register and divided clock driver, and a combined data buffer, where each of the sub-channels includes a first pseudo channel and a second pseudo channel, each pseudo channel including a plurality of dynamic random-access memory (DRAM) chips; the register and divided clock driver is configured to determine a command mode in response to a command sent by a host and send the command to the first pseudo channel and/or the second pseudo channel according to the command mode; and the combined data buffer is configured to interleave data of the first pseudo channel and the second pseudo channel According to the present disclosure, without having to change the original command sending approach, the register and divided clock driver determines various command modes in response to received commands, and then sends each command to a plurality of pseudo channels simultaneously or separately, thus achieving faster and more effective reading of data.