The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2024
Filed:
Jun. 05, 2023
Applicant:
Kioxia Corporation, Tokyo, JP;
Inventors:
Hideki Yoshida, Yokohama Kanagawa, JP;
Shinichi Kanno, Tokyo, JP;
Assignee:
Kioxia Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0616 (2013.01); G06F 3/064 (2013.01); G06F 3/0658 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 12/1009 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7207 (2013.01); G06F 2212/7208 (2013.01);
Abstract
According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.