The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Mar. 14, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Ji Hyo Kang, Icheon-si, KR;

Kyung Hoon Kim, Icheon-si, KR;

Jae Hyeok Yang, Icheon-si, KR;

Sang Yeon Byeon, Icheon-si, KR;

Gang Sik Lee, Icheon-si, KR;

Joo Hyung Chae, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G11C 7/22 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G11C 7/222 (2013.01); H03K 19/0016 (2013.01);
Abstract

A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.


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