The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Apr. 27, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Arnab Khawas, Bangalore, IN;

Gokul Sabada, Bangalore, IN;

Madhavan Sainath Rao Pissay, Hyderabad, IN;

Badarish Subbannavar, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318552 (2013.01); G01R 31/31724 (2013.01); G01R 31/31727 (2013.01);
Abstract

Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.


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