The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Jul. 16, 2020
Applicant:

Vermon SA, Tours, FR;

Inventors:

Cyril Meynier, Tours, FR;

Dominique Gross, Tours, FR;

Nicolas Senegond, Tours, FR;

Assignee:

VERMON SA, Tours, FR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B81B 3/00 (2006.01); B06B 1/02 (2006.01); B81C 1/00 (2006.01); G01N 29/24 (2006.01);
U.S. Cl.
CPC ...
B81B 3/0021 (2013.01); B06B 1/0292 (2013.01); B81C 1/00158 (2013.01); B81B 2201/0271 (2013.01); B81B 2203/0127 (2013.01); B81B 2203/0315 (2013.01); B81B 2203/04 (2013.01); B81C 2201/013 (2013.01); B81C 2201/0178 (2013.01); G01N 29/2406 (2013.01);
Abstract

The present disclosure relates to a CMUT transducer () comprising: —a conductive or semiconductor substrate () coated with a stack of one or a plurality of dielectric layers (); —a cavity () formed in said stack; —a conductive or semiconductor membrane () suspended above the cavity; —at the bottom of the cavity, a conductive region () in contact with the upper surface of the substrate, said conductive region being interrupted on a portion of the upper surface of the substrate; and—in the cavity, a stop structure () made of a dielectric material localized on or above the area of interruption of the conductive region ().


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