The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Sep. 22, 2022
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventor:

Toru Tanzawa, Tokyo, JP;

Assignee:

Lodestar Licensing Group LLC, Evanston, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 20/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/0657 (2013.01); H01L 29/785 (2013.01); H10B 20/60 (2023.02);
Abstract

Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.


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