The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Nov. 07, 2022
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventor:

Troy A. Manning, Meridian, ID (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G06F 3/06 (2006.01); G06F 7/523 (2006.01); G06F 12/00 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); H03K 19/00 (2006.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G06F 3/0611 (2013.01); G06F 3/0625 (2013.01); G06F 3/065 (2013.01); G06F 3/068 (2013.01); G06F 7/523 (2013.01); G06F 12/00 (2013.01); G11C 7/06 (2013.01); G11C 7/065 (2013.01); G11C 7/1087 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); H03K 19/0013 (2013.01); H03K 19/1776 (2013.01);
Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.


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