The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Jul. 20, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Milan Pesic, Paoli, PA (US);

Shruba Gangopadhyay, San Jose, CA (US);

Muthukumar Kaliappan, Fremont, CA (US);

Michael Haverty, Mountain View, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/065 (2023.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); G11C 11/54 (2013.01); G11C 13/0011 (2013.01); H10B 63/84 (2023.02); H10N 70/023 (2023.02); H10N 70/24 (2023.02); H10N 70/8416 (2023.02); H10N 70/8833 (2023.02);
Abstract

A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.


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