The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2024
Filed:
May. 08, 2023
Applicant:
Celera, Inc., San Jose, CA (US);
Inventors:
Assignee:
Celera, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 111/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/373 (2020.01); G06F 2111/12 (2020.01);
Abstract
Some embodiments of the present disclosure include techniques for generating a capacitor comprising receiving a total capacitance for a capacitor to be generated, determining a number N of unit capacitors having a unit capacitance to be combined to form the total capacitance, generating a transistor level schematic comprising N unit capacitor schematics having the unit capacitance, wherein the N unit capacitor schematics are configured to produce the total capacitance, and generating a layout comprising N capacitor layout elements configured to produce said capacitor.