The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Feb. 24, 2023
Applicant:

T-head (Shanghai) Semiconductor Co., Ltd., Shanghai Free Trade Area, CN;

Inventors:

Jifeng Wang, Chengdu, CN;

Yuming Xu, Chengdu, CN;

Wentao Wu, Shanghai, CN;

Fei Xue, Sunnyvale, CA (US);

Xiang Gao, Shanghai, CN;

Jiajing Jin, Hangzhou, CN;

Assignee:

T-Head (Shanghai) Semiconductor Co., Ltd., Shanghai Free Trade Area, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 2212/225 (2013.01); G06F 2212/283 (2013.01); G06F 2212/7203 (2013.01);
Abstract

This application describes systems and methods for facilitating memory access in flash drives. An example method performed by a memory controller may include receiving, from a host, a write command comprising data to be written into a flash memory; splitting the data into a first portion and a second portion; storing the first portion into a static random-access memory (SRAM) in the memory controller; storing the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller; initiating a configuration operation corresponding to the write command; fetching the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory; combining the fetched first portion and the fetched second portion; and storing the combined first portion and the second portion into the flash memory.


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