The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Feb. 01, 2023
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Niladrish Chatterjee, Kirkland, WA (US);

Zachary Joseph Susskind, Austin, TX (US);

Donghyuk Lee, Cedar Park, TX (US);

James Michael O'Connor, Austin, TX (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 3/0644 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01);
Abstract

Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.


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Chatterjee, Niladrish. (2024). Memory page access instrumentation (U.S. Patent No. 12141451). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12141451

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