Error correction circuit, error correction method, and communication apparatus

Abstract

An error correction circuit () according to this invention includes a first error correction processing circuit () configured to perform error correction processing in a row direction on array data having undergone first coding in the row direction, an error detection processing circuit () configured to perform error detection processing in a column direction on the array data having undergone second coding in the column direction, a corrected-bit likelihood calculation circuit () configured to calculate for each row the sum of likelihoods of corrected bits each of which is a bit corrected by the first error correction processing circuit (), a high-likelihood row detection circuit () configured to detect rows of the array data in the descending order of the sums of likelihoods of corrected bits of respective rows output from the corrected-bit likelihood calculation circuit (), and a second error correction processing circuit () configured to correct a bit at which a column error-detected by the error detection processing circuit () and a row detected by the high-likelihood row detection circuit () cross each other. An error correction circuit capable of improving transmission characteristics while suppressing the circuit scale can be provided.