The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Sep. 22, 2020
Applicant:

Invensense, Inc., San Jose, CA (US);

Inventors:

Daesung Lee, San Jose, CA (US);

Alan Cuthbertson, San Jose, CA (US);

Assignee:

INVENSENSE, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); B81B 3/00 (2006.01); B81C 1/00 (2006.01); G01C 19/5712 (2012.01); G01P 1/00 (2006.01); G01P 15/08 (2006.01);
U.S. Cl.
CPC ...
B81B 7/008 (2013.01); B81B 3/0005 (2013.01); B81C 1/00238 (2013.01); G01C 19/5712 (2013.01); G01P 1/00 (2013.01); G01P 15/08 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81C 2201/112 (2013.01);
Abstract

Selective self-assembled monolayer patterning with sacrificial layer for devices is provided herein. A sensor device can include a handle layer and a device layer that comprises a first side and a second side. First portions of the first side are operatively connected to defined portions of the handle layer. At least one area of the second side comprises an anti-stiction area formed with an anti-stiction coating. The device can also include a Complementary Metal-Oxide-Semiconductor (CMOS) wafer operatively connected to second portions of the second side of the device layer. The CMOS wafer comprises at least one bump stop. The anti-stiction area faces the at least one bump stop.


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