The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

Aug. 08, 2023
Applicant:

Pragmatic Printing Ltd., Sedgefield, GB;

Inventors:

Richard Price, Sedgefield, GB;

Catherine Ramsdale, Sedgefield, GB;

Brian Hardy Cobb, Sedgefield, GB;

Feras Alkhalil, Sedgefield, GB;

Assignee:

PRAGMATIC PRINTING LTD., Sedgefield, GB;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 21/3213 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1251 (2013.01); H01L 21/02266 (2013.01); H01L 21/02631 (2013.01); H01L 21/0274 (2013.01); H01L 21/2855 (2013.01); H01L 21/30604 (2013.01); H01L 21/32133 (2013.01); H01L 27/1262 (2013.01); H01L 27/127 (2013.01); H01L 27/1288 (2013.01); H01L 29/401 (2013.01); H01L 29/41733 (2013.01);
Abstract

A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.


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