The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

May. 06, 2021
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Takeshi Aoki, Ebina, JP;

Yoshiyuki Kurokawa, Sagamihara, JP;

Munehiro Kozuma, Atsugi, JP;

Takuro Kanemura, Sapporo, JP;

Tatsunori Inoue, Yamato, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 5/10 (2006.01); G11C 11/22 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
G11C 5/10 (2013.01); G11C 11/221 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 53/30 (2023.02);
Abstract

A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.


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