The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2024

Filed:

Dec. 30, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Chia-Jui Hsu, Santa Clara, CA (US);

Mukund Sivaraman, Palo Alto, CA (US);

Vinod Kathail, Palo Alto, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 8/41 (2018.01); G06F 9/54 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 8/451 (2013.01); G06F 9/544 (2013.01);
Abstract

Modeling and compiling tensor processing applications using multi-layer adaptive data flow (ML-ADF) graphs, including folding the ML-ADF graph for temporal sharing of platform resources, computing schedules for runtime orchestration of kernel execution, memory reuse, tensor and sub-volume movement, and dataflow synchronization, and generating binary code for processors of the target computing platform and re-targetable controller code. The ML-ADF graph may represent: tensor processing of a layer of a neural network as data flow through the data nodes and distribution to compute tiles across memory hierarchy; data flow amongst layers of the neural network using connections amongst data nodes of the respective layers; and multi-dimension data partitioning and distribution using tiling parameters associated with ports of the data nodes.


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