The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Jan. 04, 2023
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Rainer Stadlmair, Deutschfeistritz, AT;

Shankar Joshi, Bangalore, IN;

Raghavendra Kongari, Bangalore, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); G06K 19/07 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0337 (2013.01); G06K 19/0723 (2013.01); H04L 7/0037 (2013.01);
Abstract

There is provided, a method for clock recovery in a RFID tag, the method includes receiving a RF field from a RFID reader. A field clock is generated from the received RF field, from which a clock recovery signal is generated. The RF field is modulated to produce a RF modulation. Generation of the clock recovery signal is paused while the RF field is being modulated. A modulation envelope signal is generated and used for load modulation. Generation of the clock recovery signal at the end of the RF modulation is resumed after a delay of one clock cycle from a falling edge of the modulation envelope signal. In another embodiment of the method, instead of adding the delay, a differential amplifier is used to increase RF field detection sensitivity. The method and the RFID tag ensures synchronized resumption of a PLL clock and the clock recovery signal.


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